OpenPET Firmware Parameters¶
This section will outline the OpenPET firmware parameters in the Main, IO, and detector board field programmable gate arrays (FPGAs). These parameters are VHDL generics that can be changed during compilation.
Main FPGA¶
Entity - main¶
| Name | Type | Description |
|---|---|---|
| g_NODE_TYPE | std_logic_vector(3 downto 0) | SupportBoard Function (Type)
|
| g_slice_div | integer | Clk to slice relation.
0 (default) divide by 8.
1 means divide by 16.
|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_adc_number | positive | Number of ADC chips
|
| g_adc_resolution | positive | ADC resolution
|
| g_QUSB_FD_WIDTH | positive | QuickUSB Data bus width
|
| g_QUSB_ADR_WIDTH | positive | QuickUSB Address bus width
|
| g_QUSB_CMD_PKTS | positive | Number of QuickUSB packets
(write cycles) to complete a single
OpenPET command.
|
| g_osc_num_adc_samples | positive | Total number of ADC samples
per db
|
| g_sng_max_pipeline_stages | positive | Maximum number of pipeline
stages
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
| g_en_qusb | boolean | Enable/disable quickusb logic
|
| g_en_eth | boolean | Enable/disable ethernet logic
|
| g_eth_ip | std_logic_vector(31 downto 0) | IP address 10.10.10.2
|
| g_eth_mac | std_logic_vector(47 downto 0) | Mac address
|
| g_eth_ip_dst | std_logic_vector(31 downto 0) | IP address 10.10.10.2
|
| g_eth_mac_dst | std_logic_vector(47 downto 0) | Mac address
|
| –g_eth_ip_dst | std_logic_vector(31 downto 0) | IP address 10.10.10.2
|
| –g_eth_mac_dst | std_logic_vector(47 downto 0) | Mac address
|
| g_eth_jumbo_dw | positive | 14 for jumbo frames
11 for normal
|
| g_udp_width | positive | Width of UDP bus
|
Component¶
qusb¶
| Name | Type | Description |
|---|---|---|
| g_FD_WIDTH | positive | QuickUSB Data bus width
|
| g_ADR_WIDTH | positive | QuickUSB Address bus width
|
| g_CMD_PKTS | positive | Number of QuickUSB packets (write cycles)
to complete a single OpenPET command
|
| g_DATA_FIFO_DEPTH | positive | Depth of output data FIFO
|
swfw_cmd¶
| Name | Type | Description |
|---|---|---|
| g_NODE_TYPE | std_logic_vector(3 downto 0) | SupportBoard Function (Type)
|
| g_osc_num_adc_samples | positive | Total number of ADC samples
per db
|
| g_adc_number | positive | Number of ADC chips
|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_sng_max_pipeline_stages | positive | Maximum number of pipeline
stages
|
| g_en_tdc | boolean | Enable/disable TDC logic
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
processdata¶
| Name | Type | Description |
|---|---|---|
| g_NODE_TYPE | std_logic_vector(3 downto 0) | SupportBoard Function (Type)
|
| g_osc_fifo_depth | positive | Oscilloscope FIFO depth
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
ether_rgmii¶
| Name | Type | Description |
|---|---|---|
| g_ip_src | std_logic_vector(31 downto 0) | Default source IP
|
| g_mac_src | std_logic_vector(47 downto 0) | Default source mac
|
| g_ip_dst | std_logic_vector(31 downto 0) | Default destination IP
|
| g_mac_dst | std_logic_vector(47 downto 0) | Default destination mac
|
| g_jumbo_dw | positive | Jumbo frames
|
| g_udp_width | positive | Width of data bus
|
| g_osc_num_adc_samples | positive | Depth of output data FIFO
|
IO FPGA¶
Entity - io¶
| Name | Type | Description |
|---|---|---|
| g_NODE_TYPE | std_logic_vector(3 downto 0) | SupportBoard Function (Type)
|
| g_slice_div | integer | Clk to slice relation.
0 (default) divide by 8.
1 means divide by 16.
|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_adc_number | positive | Number of ADC chips
|
| g_adc_resolution | positive | ADC resolution
|
| g_osc_num_adc_samples | positive | Total number of ADC samples
per db
|
| g_sng_max_pipeline_stages | positive | Maximum number of pipeline
stages
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
Component¶
swfw_cmd¶
| Name | Type | Description |
|---|---|---|
| g_osc_num_adc_samples | positive | Total number of ADC samples
per db
|
| g_adc_number | positive | Number of ADC chips
|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_en_tdc | boolean | Enable/disable TDC logic
|
| g_frame_width | positive | ADCClk_Freq / SliceClk_Freq
|
| g_sng_max_pipeline_stages | positive | Maximum number of pipeline
stages
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
processdata¶
| Name | Type | Description |
|---|---|---|
| g_NODE_TYPE | std_logic_vector(3 downto 0) | SupportBoard Function (Type)
|
| g_osc_fifo_depth | positive | Oscilloscope FIFO depth
|
| g_frame_width | positive | ADCClk_Freq / SliceClk_Freq
|
| g_sng_max_pipeline_stages | positive | Maximum number of pipeline
stages
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
Detector Board FPGA¶
Entity - db16ch¶
| Name | Type | Description |
|---|---|---|
| g_en_debug | boolean | Enable/disable debugging
|
| g_slice_div | integer | Clk to slice relation.
0 (default) divide by 8.
1 means divide by 16.
|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_adc_number | positive | Number of ADC chips
|
| g_adc_resolution | positive | ADC resolution
|
| g_tdc_type | integer | Generate TDC logic. 0=no logic
1=waveunion, 2=multiphase (default)
|
| g_tdc_resolution | positive | TDC resolution
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_osc_num_adc_samples | positive | Total number of ADC samples
per run
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
| g_sng_max_pipeline_stages | positive | Maximum number of pipeline
stages
|
Component¶
swfw_cmd¶
| Name | Type | Description |
|---|---|---|
| g_osc_num_adc_samples | positive | Total number of ADC samples
per db
|
| g_adc_number | positive | Number of ADC chips
|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_frame_width | positive | ADCClk_Freq / SliceClk_Freq
|
| g_sng_max_pipeline_stages | positive | Maximum number of pipeline
stages
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
adc_16ch¶
| Name | Type | Description |
|---|---|---|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_adc_number | positive | Number of ADC chips
|
| g_adc_resolution | positive | ADC resolution
|
processdata¶
| Name | Type | Description |
|---|---|---|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_adc_number | positive | Number of ADC chips
|
| g_adc_resolution | positive | ADC resolution
|
| g_tdc_resolution | positive | TDC resolution
|
| g_osc_fifo_depth | positive | Oscilloscope FIFO depth
|
| g_frame_width | positive | ADCClk_Freq / SliceClk_Freq
|
| g_sng_max_pipeline_stages | positive | Maximum number of pipeline
stages
|
| g_tdc_type | integer | Generate TDC logic. 0=no logic
1=waveunion, 2=multiphase (default)
|
| g_en_osc_mode | boolean | Generate oscilloscope mode logic
|
| g_sng_mode_type | integer | Generate singles mode logic.
0=no logic generated.
1=LBNL example (default)
|
tcd¶
| Name | Type | Description |
|---|---|---|
| g_en_debug | boolean | Enable/disable debugging
|
| g_tdc_type | integer | Generate TDC logic. 0=no logic
1=waveunion, 2=multiphase (default)
|
| g_adc_channels | positive | Number of ADC channels to
deserialize
|
| g_adc_number | positive | Number of ADC chips
|
| g_tdc_resolution | positive | TDC resolution
|
sram¶
| Name | Type | Description |
|---|---|---|
| g_dataw | positive | Data width
|
| g_addrw | positive | Address width
|